------------------------------------------------//库声明
LIBRARY IEEE; 
USE IEEE.STD_LOGIC_1164.ALL; 
USE IEEE.STD_LOGIC_UNSIGNED.ALL; 
USE IEEE.STD_LOGIC_ARITH.ALL;

------------------------------------------------//实体定义
entity led_display is
port(
        clk_in : in std_logic;
	 led_change : in integer;
           led : out std_logic
    );
end entity;

------------------------------------------------//结构体定义
architecture behave of led_display is

------------------------------------------------//信号量定义
signal clk_1Mhz : std_logic;
signal clk_1hz : std_logic;
signal count_1: integer range 0 to 50;
signal count_2: integer range 0 to 1000000;
signal rom_zhi: integer range 0 to 12;
signal count_3: integer range 0 to 12;
signal led_temp_1 : std_logic;
signal led_temp_2 : std_logic;
signal count_4: integer range 1 to 2;

begin

------------------------------------------------//进程1，分频，产生1Mhz
    process(clk_in)
    begin
        if rising_edge(clk_in) then
             if count_1=50 then
                   count_1<=0;
                    clk_1Mhz<='1';
             else
                count_1<=count_1+1;
                   clk_1Mhz<='0';
             end if;
         end if;
    end process;
   
------------------------------------------------//进程2，分频，产生1hz	
    process(clk_1Mhz)
    begin
        if rising_edge(clk_1Mhz) then
             if count_2=1000000 then
                   count_2<=0;
                    clk_1hz<='1';
             else
                count_2<=count_2+1;
                   clk_1hz<='0';
             end if;
         end if;
    end process;

------------------------------------------------//进程3，产生rom_zhi
    process(clk_1hz)
    begin
        if rising_edge(clk_1hz) then
             if rom_zhi=12 then
                   rom_zhi<=0;          
             else
                rom_zhi<=rom_zhi+1;
             end if;
         end if;
    end process;

------------------------------------------------//进程4，计数 
	 process(clk_1Mhz)
    begin
        if rising_edge(clk_1Mhz) then
             if count_3=12 then
                   count_3<=0;          
             else
                count_3<=count_3+1;
             end if;
         end if;
    end process;
	 
	 process(clk_1hz,led_change)
	 begin
    	 if count_3<rom_zhi then
           led_temp_1<='1';
       else
           led_temp_1<='0';
       end if;
		 
		 if rising_edge(clk_1hz) then
           if count_4=2 then
               count_4<=1;          
           else
               count_4<=count_4+1;
           end if;
			  if count_4=1 then
			      led_temp_2<='1';
			  else
			      led_temp_2<='0';
			  end if;
       end if;
		 
		 
		 if led_change=0 then
           led <= led_temp_1;
       else led <= led_temp_2;
       end if;
	 end process;

end behave;